The present invention relates to control method and apparatus of modular design for regulating the harmonics contents of the current drawn from the power line by electrical equipment and loads, and in particular to the electronic circuit design, physical construction and layout of such an apparatus.
Switch Mode and Resonant Converters are widely used for DC-DC, DC-AC, AC-DC and AC-AC conversion. In some groups of applications, the purpose of the power conversion scheme is to shape the input current seen at the input of the converter. For example, in an input power stage known in the art as an Active Power Factor Correction (APFC) circuit, the function of the converter is to ensure that the AC current seen by the power line is in phase with the line voltage with minimum high order harmonics. A typical well-known embodiment of APFC is shown in FIG. 1. In this method, the input voltage is rectified by a diode bridge Dxe2x80x21 and fed to a Boost stage that comprises an input inductor Lxe2x80x2in, a power switch Sxe2x80x21, a high frequency rectifier Dxe2x80x22, an output filter capacitor Cxe2x80x2O and a load Rxe2x80x2L. Power switch Sxe2x80x21 is driven by a high frequency control signal of duty cycle DON such as to force an input current iina to follow the shape of a rectified input voltage vinR. Consequently, the input terminal will look resistive i.e. the Power Factor (PF) will be unity.
The need for APFC stages is driven by the worldwide concern for the quality of the power line supplies. Injection of high harmonics into the power line and poor power factor in general, is known to cause many problems. Among these are the lower efficiency of power transmission, possible interference to other units connected to the power line, and distortion of the line voltage shape that is undesirable. In the light of the practical importance of APFC many countries have adopted, or are in the process of adopting, voluntary and mandatory standard. These norms set limits to the permissible current line harmonics injected by any given equipment that is powered by the mains so as to maintain a high power-quality [International Electrotechnical Commission (IEC), xe2x80x9cInternational Standard 1000-3-2,xe2x80x9d pp. 1-47, 1995].
Another advantage of APFC is the increase in the power level than can be drawn from a given power line. Without Power Factor Correction, the rms current will be higher than the magnitude of the first harmonics of the current, the latter being the only component that contributes to real load power. However, protection elements such as fuses and circuit breakers respond to the rms current. Consequently, the rms current will limit the maximum power that can be drawn from the line. In Power Factor Corrected equipment the rms current equals the magnitude of the first harmonics of the current (since the higher harmonics are absent) and hence the power drawn from the line could reach the maximum theoretical value. It is thus evident that the need for APFC circuits is wide spread, and that the economics of the realization is of prime importance. Cost is of great concern considering the fact that the APFC is an add-on expense to the functionality of the original equipment in which the APFC stage is included. In the light of the above, physical construction methods of APFC that are economical to produce and can be easily integrate in any given equipment are highly desirable and advantageous.
FIG. 2 illustrates the conventional embodiment of a APFC system [R. Mamano, xe2x80x9cNew developments in high power factor circuit topologies,xe2x80x9d HPFC Record, pp. 63-74, 1996.]. An APF CONTROLLER receives the shape of a rectified power line voltage Vacxe2x80x94ref obtained via a divider 110 comprised of resistors Rxe2x80x2a and Rxe2x80x2b from an input voltage VinR, which shape is used as the reference for the desired shape of the input current. The controller also receives a voltage viin across a resistor Rxe2x80x2s, the voltage Viin being identical to the input current when the power switch is on, and generates gate pulses DON to a power switch Qxe2x80x21 such as to force the inductor current to follow the reference. The current level is adjusted for any given load Rxe2x80x2L by monitoring output voltage VO via a divider 120 comprised of resistors Rxe2x80x21 and Rxe2x80x22, and by multiplying the reference signal Vacxe2x80x94ref by the deviation from the desired output voltage level, so as to trim the effective reference signal to the load.
A major drawback of the prior art implementation of the APFC is the need for sensing the input voltage VinR, namely the line voltage after rectification. Due to the switching effects, the input voltage is normally noisy and is susceptible to interference pick-up that may distort the reference signal and hence the input current. Furthermore, the extra pin required for input voltage sensing will increase the number of pins of a modular device built in the conventional APFC scheme.
PFC controllers that do not require the sensing of the input voltage have been described in the past. (S. Ben Yaakov and I. Zeltser, xe2x80x9cPWM Converters with Resistive Inputxe2x80x9d, IEEE Trans. Industrial Electr., Vol. 45 (3), pp. 519-520, 1998; S. Ben Yaakov and I. Zeltser, xe2x80x9cPWM Converters with Resistive Inputxe2x80x9d,PCIM-98, pp. 87-95, Nuremberg, 1998; U.S. Pat. No. 5,742,151 to Hwang; and U.S. Pat. No. 6,034,513 to Ferrington). However, prior art methods that do not sense the input voltage suffer from a number of drawbacks that deteriorate their performance, in particular resulting in a higher Total Harmonic Distortion (THD). Furthermore, these prior art methods do not include means to ensure soft switching of the main switch. This deficiency is a major drawback in high power applications, where the reverse recovery current of the main diode may cause substantial power losses and high stresses on the main diode and switch. These drawbacks are next discussed in connection with the circuit described in S. Ben Yaakov and I. Zeltser, PCIM-98, but they apply in whole or part to other prior art embodiments of APFC systems that do not employ input voltage sensing.
The operation of the controller described in S. Ben Yaakov and I. Zeltzer, PCIM-98, hinges on some basic theoretical considerations to be detailed first. Consider the Boost stage of FIG. 1. The voltage seen at point xe2x80x98axe2x80x99 is a pulsating voltage of maximum amplitude Vo and duration of toff (when Sxe2x80x21 is not conducting). Consequently, the average voltage vav at point xe2x80x98axe2x80x99 will be:                               v          av                =                                            V              o                        ⁢                          t              off                                            t            S                                              (        1        )            
where tS is the PWM switching period.
Or:
vav=VoDOFFxe2x80x83xe2x80x83(2) 
where                               D          OFF                =                              t            off                                t            s                                              (        3        )            
The xe2x80x98onxe2x80x99 duty cycle DON, when Sxe2x80x21 is conducting (During ton) is similarly defined as:                               D          ON                =                              t            on                                t            s                                              (        4        )            
The input voltage fed to the Boost converter, is assumed to be of low frequency as compared to the switching frequency (fS=1/tS) and hence can be considered constant over one or several switching periods (tS). Assuming that the power stage is properly controlled, the average low frequency voltage across Lxe2x80x2in, will be close to zero (otherwise the current will increase to very high values). This implies:
vinR=vavxe2x80x83xe2x80x83(5) 
or from (1)
vinR=VoDOFFxe2x80x83xe2x80x83(6) 
If DOFF is programmed according to the rule:
DOFF=Kiinaxe2x80x83xe2x80x83(7) 
where K is a constant and iina is the low frequency component of the input current (iin), then:
vinR=VoKiinaxe2x80x83xe2x80x83(8) 
or:                               i          ina                =                              v            inR                                              V              o                        ⁢            K                                              (        9        )            
Assuming now that Cxe2x80x2O is sufficiently large so that the ripple of Vo can be neglected one sees that, according to eq. (8), the input current will follow the input voltage. That is, the converter stage will look resistive with an apparent input resistance Re:
Re=KVoxe2x80x83xe2x80x83(10) 
The value of the input resistance and hence the input current can thus be controlled by varying K. In practical applications, Vo needs to be maintained constant even if the load (Rxe2x80x2L) varies. In this control scheme, the output voltage can be maintained constant by closing a feedback loop on K. This is shown conceptually in FIG. 3. Here, the voltage that is proportional to viin is multiplied in a multiplier (M) by the output Ve of an error amplifier AMP1xe2x80x2 that compares Vo to a reference voltage Vref. The product, which is proportional to iina by a given factor K is fed to a PWM modulator to generate DOFF according to eq. (7).
As known in the art, e.g. in S. Ben Yaakov and I. Zeltser, PCIM-98, a PWM modulator that is based on a controller having a ramp with a variable slope can replace the function of multiplier (M) in FIG. 3. The basic configuration of a PWM modulator that is based on a controller having a ramp with a variable slope is shown in FIG. 4. It includes a ramp generator built around a capacitor Cramp, a current dependent source G1 and a discharge switch Sds. The controller also includes a comparator COMP1 that is used as a PWM modulator. COMP1 actually generates a PWM signal. The output of comparator COMP1 is fed via a proper driver to the control terminal of the main switch of the power stage (power switch Sxe2x80x21 in FIG. 1). The basic switching cycle (tS), see also FIG. 5, is controlled by a CLOCK that produces sharp pulses that are used to discharge ramp capacitor Cramp. The slope of the ramp (xe2x80x9cSLOPExe2x80x9d) is governed by the output current (IG) of current source G1. Hence SLOPE will be:                     SLOPE        =                              I            G                                C            ramp                                              (        11        )            
A voltage proportional to the input current (viin=Ki iina) (where K1 is actually the resistance of Rxe2x80x2s) is compared to the ramp voltage at the input of comparator COMP1 to produce toff such that:
toffSLOPE=viinxe2x80x83xe2x80x83(12) 
Consequently:                               t          off                =                              v            iin                    SLOPE                                    (        13        )            
Or:
toff=Kiinaxe2x80x83xe2x80x83(14) 
where:                     K        =                                            K              i                        ⁢                          C              ramp                                            I            G                                              (        15        )            
It is thus evident that the basic circuit of FIG. 4 implements the control rule of eq. (7) and thus causes the input terminals of the Boost converter (FIG. 1) to look resistive. Furthermore, the implementation of FIG. 4 will also automatically maintain a constant output voltage as needed in many applications. This is accomplished by making the dependent current source a function of the difference between reference voltage Vref and output voltage Vo (FIG. 4). This is similar to amplifier AMP1xe2x80x2 of FIG. 3, except that G1 is now a transconductance amplifier, namely that its output is a current that is proportional to the voltage at its input terminals. Consequently, when there is a tendency for an output voltage change, say a decrease due to an increase in load current, the magnitude of IG will increase in such a way as to make K smaller and hence iin larger. This is next discussed in detail by considering the curves of FIG. 5.
Consider a case in which the steady state conditions correspond to some input current iina1 (that is translated to a proportional voltage viin1). The respective steady state duty cycle is DON1. Now suppose there is an increase in load current which results in a lower VO. The tranconductance amplifier (G1, FIG. 4) will react and its output current (IG) will increase. This will cause the voltage slope across Cramp to increase from an initial ramp value of SLOPE1 to a steeper value of SLOPE2 (FIG. 5). As a result the xe2x80x9conxe2x80x9d part of the switching duty cycle will change from the initial value of ton1 to a new, larger value ton2. As known in the art, this will increase the input current. Eventually, the system will settle at a new operating point with a higher input current (viin2) corresponding to the higher power demand, but with the same xe2x80x9conxe2x80x9d duty cycle (ton1), which is a function of the steady state voltage ratio.
As pointed out above, the prior art realization of APFC systems with no sensing of input voltage suffer from a number of drawbacks that lead to inferior performance. These major deficiencies are discussed below.
A major problem that causes an increase in the undesired input current harmonics, is the modulation of the duty cycle by the ripple of the output voltage. Since the output voltage includes a ripple component, the current IG (FIG. 4) will include a ripple component as well. This will cause a distortion on the input current iina. The problem could be amended to some extent by slowing down the response of G1 so as to attenuate the ripple component. However this will result in large undesired overshoots and undershoots in the output voltage in response to load changes.
Another drawback of the prior art solutions is the distortion of the input current due to errors in the realization of the basic relationship given by eq. (7). For example, assume that the ramp voltage on Cramp (FIG. 4) is as shown by trace 200 in FIG. 6, resulting from the charging current IG and the discharge pulse Vdis 202 (FIG. 6) fed to Sds (FIG. 4). Consequently, the effective off-time toff generated by the circuit (and fed to the main switch) will be composed of the time segments t0xe2x88x92t4 
toff(t1xe2x88x92t0)+(t4xe2x88x92t3)+(tsxe2x88x92t4)xe2x80x83xe2x80x83(16) 
Or:                               t          off                =                                            v              iin                                      S              1                                +                                    v              iin                                      S              2                                +                      (                                          t                s                            -                              t                4                                      )                                              (        17        )            
Since viin=Kin iina we find                               D          OFF                =                                                                              K                  in                                ⁢                                  i                  ina                                                            t                s                                      ⁢                          (                                                1                                      S                    1                                                  +                                  1                                      S                    2                                                              )                                +                                    (                                                t                  s                                -                                  t                  4                                            )                                      t              s                                                          (        18        )            
That is, the actual toff will deviate from the theoretical relationship (eq. 7) due to the last term in eq. (18). This will introduce distortion to the input current iina.
Another drawback of the prior art solutions using APFC systems without input voltage sensing is the hard switching of the main switch at xe2x80x9cturn-onxe2x80x9d. During turn-on, main switch Qxe2x80x21 has to absorb the very high reverse recovery current of main diode Dxe2x80x22 (FIG. 3). Considering the high output voltage of the APFC power stage, the peak reverse current could be very high, stressing both the switch and the diode.
The above examples show that the prior art solutions to an APFC stage that does not require the sensing of the input voltage have considerable practical drawbacks.
There is thus a widely recognized need for, and it would be highly advantageous to have, APFC units, which does not require the sensing of the input voltage but does have a low input current distortion. It will be further highly desirable that the circuit will reduce the stresses due to the reverse recovery process of the main diode. Also, it would be highly advantageous to have an APFC unit of modular construction, that is also compatible with microelectronics technology. These goals are met by present invention.
The present invention discloses an innovative method for realizing an Active Power Factor Correction (APFC) stage that reduces line distortion by: (a) making toff meet accurately equation (7); (b) reducing the effect of the output ripple; and (c) eliminating the harmful effects of the reverse recovery of the main diode.
An important feature of the method is the lack of a sense line to the input voltage of the APFC stage. This makes the stage less sensitive to noise and facilitates a modular construction of the electronics in either monolithic or discrete implementation. These features reduce the cost of APFC stages built according to this invention and improving their performance.
According to the present invention there is provided a method for reducing the harmonics contents of an input current drawn from a power line into an electrical system without sensing an input voltage, the method comprising: providing an active power factor correction controller with a switch module having a main switch and a timing device, wherein the main switch has an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, and maintaining a linear relationship between the off-duty cycle duration and the input current by using the timing device.
According to the present invention there is provided an apparatus for active power factor correction with minimum input current distortion, comprising: an active power factor correction assembly that includes a main switch and a timing device, wherein the main switch has associated therewith an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, and wherein the timing device generates the mentioned on-time and off-time, and linearization means for maintaining a linear relation between the off-duty cycle duration and the input current.
A main innovative feature of the method according to the present invention is the application of control methods that lower the number of interconnections, and the combining of the switch and associated control circuitry in one module. These enable the construction of a complete APFC stage from five basic and independent elements: the input rectifier, inductor, switch module, output diode and output capacitor. Alternatively, by including the diode within the main switch assembly, the number of components for a complete system is reduced to four. Since no back interconnection is required, the power flow is simple, causing minimum interference to other parts of the equipment. At the same time, the streamlined construction minimizes the susceptibility of the circuit to switching noises and hence improved the stability and reliability of the circuit. An important feature of the method according to this invention is its compatibility with microelectronics technology. In particular, the switch and control module, with or without the output diode, can be produced by conventional Silicon based IC technology, making this sub-assembly a relatively low cost component. The invention also provides a cost effective solution to the problem of generating efficiently a local supply voltage needed to power the internal circuitry of the switch module. This is of particular importance in high power level applications in which the local power supply needs to sustain relatively high currents.
Therefore, according to the present invention there is provided a method for optimizing the design of APFC stages in the sense that the APFC can be assembled from basic building blocks that are easy to mount, have high reliability, potentially lower cost and highly compatible with common heat removal methods such as heat sinks and fan cooling.
The control strategy and constructional method according to this invention thereby overcome the shortcoming of existing design and control methods which include many interconnected components, signal differentiating or a costly single module with poor heat management capabilities.